pca8550 nonvolatile 5-bit register with i 2 c interface scps050a march 1999 revised april 1999 1 post office box 655303 ? dallas, texas 75265 epic ? (enhanced-performance implanted cmos) submicron process useful for jumperless configuration of pc motherboard inputs accept voltages to 5.5 v mux out signals are 2.5-v outputs non-muxed out signal is a 3.3-v output minimum of 1000 write cycles minimum of 10 years data retention package options include plastic small-outline (d), shrink small-outline (db), and thin shrink small-outline (pw) packages description this 4-bit 1-of-2 multiplexer with i 2 c input interface is designed for 3-v to 3.6-v v cc operation. the pca8550 is designed to multiplex four bits of data from parallel inputs or from i 2 c input data stored in a nonvolatile register. an additional bit of register output also is provided, which is latched to prevent changes in the output value during the write cycle. the factory default for the contents of the register is all low. these stored values can be read from, or written to, using the i 2 c bus. the ability to control writing to the register is provided by the write protect (wp) input. the override (override ) input forces all the register outputs to a low. this device provides a fast-mode (400 kbit/s) or standard-mode (100 kbit/s) i 2 c serial interface for data input and output. the implementation is as a slave. the device address is specified in the i 2 c interface definition table. both of the i 2 c schmitt-trigger inputs (scl and sda) provide integrated pullup resistors and are 5-v tolerant. the pca8550 is characterized for operation from 0 c to 70 c. function table inputs outputs mux select override mux out non-muxed out l l l l l h nonvolatile register nonvolatile register h x mux in latched non-muxed out 2 2 the latched non-muxed out state is the value present on the non-muxed out output at the time the mux select input transitions from the low to the high state. copyright ? 1999, texas instruments incorporated production data information is current as of publication date. products conform to specifications per the terms of texas instruments standard warranty. production processing does not necessarily include testing of all parameters. please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. epic is a trademark of texas instruments incorporated. 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 i 2 c scl i 2 c sda override mux in a mux in b mux in c mux in d gnd v cc wp non-muxed out mux select mux out a mux out b mux out c mux out d d, db, or pw package (top view)
pca8550 nonvolatile 5-bit register with i 2 c interface scps050a march 1999 revised april 1999 2 post office box 655303 ? dallas, texas 75265 logic diagram (positive logic) 5-bit nonvolatile register i 2 c interface logic address: 1001110 1-bit transparent latch 4-bit 1-of-2 multiplexer non-muxed out mux out a mux out b mux out c mux out d mux in a scl sda override wp mux in b mux in c mux in d mux select v cc v cc v cc v cc v cc 1 2 15 3 4 5 6 7 13 14 12 11 10 9
pca8550 nonvolatile 5-bit register with i 2 c interface scps050a march 1999 revised april 1999 3 post office box 655303 ? dallas, texas 75265 i 2 c interface i 2 c communication with this device is initiated by a master sending a start condition, a high-to-low transition on the serial data (sda) input/output while the serial clock (scl) input is high. after the start condition, the device address byte is sent, msb first, including the data-direction bit (r/w ). this device does not respond to the general call address. after receiving the valid address byte, this device responds with an acknowledge, a low on the sda input/output during the high of the acknowledge-related clock pulse. the data byte follows the address acknowledge. if the r/w bit is high, the data from this device are the values read from the nonvolatile register. if the r/w bit is low, the data are from the master, to be written into the register. a valid data byte is one in which the three high-order bits are low. the first valid data byte that is received is written into the register, following the stop condition. if an invalid data byte is received, it is acknowledged, but is not written into the register. the data byte is followed by an acknowledge sent from this device. if other data bytes are sent from the master following the acknowledge, they are ignored by this device. a stop condition, a low-to-high transition on the sda input/output while the scl input is high, is sent by the master. if the wp input is low during the falling edge of the first valid data byte acknowledge on the scl input and the r/w bit is low, the stop condition causes the i 2 c interface logic to write the data byte value into the nonvolatile register. data are written only if complete bytes are received and acknowledged. writing to the register takes time (t wr ), during which the device does not respond to its slave address. if the wp input is high, the i 2 c interface logic does not write to the register. i 2 c interface definition table byte bit byte 7 (msb) 6 5 4 3 2 1 0 (lsb) address h l l h h h l r/w data l l l non- muxed out mux out d mux out c mux out b mux out a absolute maximum ratings over operating free-air temperature range (unless otherwise noted) 2 supply voltage range, v cc 0.5 v to 6.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input voltage range, v i (see note 1) 0.5 v to 6.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output voltage range, v o (sda) (see note 1) 0.5 v to 6.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output voltage range, v o (mux out outputs) (see note 1) 0.5 v to 2.9 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . output voltage range, v o (non-muxed out output) (see notes 1 and 2) 0.5 v to v cc + 0.5 v . . . . . . . . . input clamp current, i ik (v i < 0 ) 50 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output clamp current, i ok (v o < 0 or v o > v cc ) (see note 2) 50 ma, +10 ma . . . . . . . . . . . . . . . . . . . . . . . . input/output clamp current, i ok (v o < 0) 50 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . continuous output current, i o (v o = 0 to v cc ) (see note 2) 15 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . continuous current through v cc or gnd 30 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . package thermal impedance, q ja (see note 3): d package 113 c/w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . db package 131 c/w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pw package 149 c/w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature range, t stg 65 c to 85 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 stresses beyond those listed under aabsolute maximum ratingso may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated under arecommended operating conditi onso is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. notes: 1. the input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are obser ved. 2. the value of v cc is provided in the recommended operating conditions table. 3. the package thermal impedance is calculated in accordance with jesd 51.
pca8550 nonvolatile 5-bit register with i 2 c interface scps050a march 1999 revised april 1999 4 post office box 655303 ? dallas, texas 75265 recommended operating conditions min max unit v cc supply voltage 3 3.6 v scl, sda 2.7 4 v ih high-level input voltage override , mux in, mux select, wp 2 4 v scl, sda 0.5 0.9 v il low-level input voltage override , mux in, mux select, wp 0.5 0.8 v i oh high-level output current mux out, non-muxed out 2 ma sda 6 i ol low-level output current mux out, non-muxed out 2 ma d t/ d v input transition rise or fall rate override , mux in, mux select, wp 10 ns/v t a operating free-air temperature 0 70 c electrical characteristics over recommended operating free-air temperature range, v cc = 3.3 v 0.3 v (unless otherwise noted) parameter test conditions min max unit v ik input diode clamp voltage i i = 18 ma 1.5 v v hys 2 scl, sda 0.19 v mux out i oh = 100 m a 2 2.625 v oh mux out i oh = 1 ma 1.7 2.625 v v oh non muxed out i oh = 100 m a 2.4 3.6 v non - muxed out i oh = 2 ma 2 3.6 mux out i ol = 100 m a 0.3 0.4 mux out i ol = 2 ma 0.3 0.7 v ol non muxed out i ol = 100 m a 0.5 0.4 v v ol non - muxed out i ol = 2 ma 0.5 0.7 v sda i ol = 3 ma 0.4 sda i ol = 6 ma 0.6 scl, sda 1.5 12 m a i ih override , mux select, wp v ih = 2.4 v 20 100 m a mux in 0.166 0.75 ma scl, sda 7 32 m a i il override , mux select, wp v il = 0.4 v 86 267 m a mux in 0.72 2 ma i cc during read or write cycle v i = 0 to v cc , i o = 0, v cc = 3.3 v 10 ma i cc not during read or write cycle v i = v cc , i o = 0 500 m a c i v i = v cc or gnd 10 pf 2 v hys is the hysteresis of schmitt-trigger inputs.
pca8550 nonvolatile 5-bit register with i 2 c interface scps050a march 1999 revised april 1999 5 post office box 655303 ? dallas, texas 75265 nonvolatile storage specifications parameter specifications write time (t wr ) 10 ms, typical memory-cell data retention 10 years, minimum maximum number of memory-cell write cycles 1000 cycles, minimum i 2 c interface timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see figure 1) v cc = 3.3 v 0.3 v unit min max unit f scl i 2 c clock frequency 10 400 khz t sch i 2 c clock high time 600 ns t scl i 2 c clock low time 1.3 m s t sp i 2 c spike time 0 50 ns t sds i 2 c serial data setup time 100 ns t sdh i 2 c serial data hold time 0 900 ns t icr i 2 c input rise time 20 300 ns t icf i 2 c input fall time 20 300 ns t ocf i 2 c output fall time (10-pf to 400-pf bus) 20 + 0.1 c b 2 250 ns t buf i 2 c bus free time between stop and start 1.3 m s t sts i 2 c start or repeated start condition setup 600 ns t sth i 2 c start or repeated start condition hold 600 ns t sps i 2 c stop condition setup 600 ns c b 2 i 2 c bus capacitive load 400 pf 2 c b = capacitance of one bus line in pf. switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see figure 2) parameter from (input) to (output) v cc = 3.3 v 0.3 v unit (input) (output) min max t mpd mux input to output propagation delay mux in mux out 20 ns t sov mux select to output valid mux select output valid 22 ns t ovn override to non-muxed out output delay override non-muxed out 15 ns t ovm override to mux out output delay override mux out 25 ns t su setup time wp falling edge of first valid data byte acknowledge on the scl input 30 ns t h hold time wp falling edge of first valid data byte acknowledge on the scl input 120 ns t r output rise time 1 3 ns/v t f output fall time 1 3 ns/v
pca8550 nonvolatile 5-bit register with i 2 c interface scps050a march 1999 revised april 1999 6 post office box 655303 ? dallas, texas 75265 parameter measurement information dut r l = 1 k w v o = 3.3 v c l = 10 pf or c l = 400 pf gnd t buf t icr t sth t sds t sdh t icf t icr t scl t sch t sts t phl t plh 0.7 v cc stop condition t sps repeat start condition start or repeat start condition scl sda start condition (s) bit 7 msb bit 6 bit 0 lsb (r/w ) acknowledge (a) stop condition (p) 2 bytes for complete device programming load circuit voltage waveforms t icf stop condition (p) t sp t su wp 2.7 v 0 v 1.5 v 1.5 v t h 0.3 v cc 0.7 v cc 0.3 v cc byte description 1 i 2 c address 2 nonvolatile register data figure 1. i 2 c interface load circuit and voltage waveforms
pca8550 nonvolatile 5-bit register with i 2 c interface scps050a march 1999 revised april 1999 7 post office box 655303 ? dallas, texas 75265 parameter measurement information from output under test c l = 15 pf (see note a) load circuit voltage waveforms propagation delay times for muxed out outputs t plh t phl 2.7 v 0 v input output (see note e) notes: a. c l includes probe and jig capacitance. b. all input pulses are supplied by generators having the following characteristics: prr 10 mhz, z o = 50 w , t r 2.5 ns, t f 2.5 ns. c. the outputs are measured one at a time with one transition per measurement. d. t plh and t phl are the same as t sov and t ovn . e. t plh and t phl are the same as t mpd , t sov , and t ovm . 1.5 v 1.5 v 1.25 v 1.25 v voltage waveforms propagation delay times for non-muxed out output t plh t phl 2.7 v 0 v input output (see note d) 1.5 v 1.5 v 1.5 v 1.5 v v oh v ol v oh v ol figure 2. load circuit and voltage waveforms
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